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SX1210
ADVANCED COMMUNICATIONS & SENSING
3.3. Receiver Description
The SX1210 is set to receive mode when MCParam_Chip_mode = 011.
First down-
conversion
Second down-
conversion
RSSI
OOK
demod
Bit
synchronizer
Control logic
-Pattern recognition
-FIFO handler
-SPI interface
-Packet handler
LNA
RF
LO1 Rx
IF1
LO2 Rx
FSK
demod
Baseband, IF2 in OOK
Figure 8: Receiver Architecture
3.3.1. Architecture
The SX1210 receiver employs a super-heterodyne architecture. Here, the first IF is 1/9 th of the RF frequency
(approximately 100MHz). The second down-conversion down-converts the I and Q signals to base band in the
case of the FSK receiver (Zero IF) and to a low-IF (IF2) for the OOK receiver.
Second
down-conversion
LO2
Rx
First
down-conversion
0
IF2=0
in FSK
IF1
≈ 100MHz
Image
frequency
LO1 Rx
Channel
Frequencyl
mode
Figure 9: FSK Receiver Setting
First
Second
down-conversion
down-conversion
IF2<0
in FSK
0
IF1
≈ 100MHz
LO2 Rx
Image
frequency
LO1 Rx
Channel
Frequency
mode
e qual to fo
Figure 10: OOK Receiver Setting
After the second down-conversion stage, the received signal is channel-select filtered and amplified to a level
adequate for demodulation. Both FSK and OOK demodulation are available. Finally, an optional Bit Synchronizer
(BitSync) is provided, to be supply a synchronous clock and data stream to a companion uC in Continuous mode,
Rev 2– Sept 8 , 2008
th
Page 17 of 73
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